1. Field of the Invention
The present invention relates to an electrically programmable non-volatile memory type integrated circuit with option configuration register. It can be applied especially but not exclusively in the field of EPROMs.
An integrated circuit with memory generally offers a certain number of options to the user. Depending on his application, the user will thus select one option or another. He may for example choose between a crystal oscillator or a ring oscillator (RC) or he may choose between a hardware watchdog or software watchdog function or he may choose to enable or disable a read protection for all or a part of the contents of the memory or again he may select an input/output port among several possibilities. This list of options is not exhaustive and many other options are offered in practice. To each option, therefore, there must correspond one or more configuration bits. These bits are contained in an option configuration register made by means of cells of the memory, arranged in the form of bistable cells.
At the end of the manufacture of the integrated circuit, it must be tested completely in every possible configuration before being supplied to the user. To perform this test, it is necessary therefore to program the option configuration register suitably for each configuration.
For the cells of a one-time programmable memory (OTP memory), it is not possible to proceed in this way by successive operations for the programming of all the possible combinations. This is why testing means are associated with the bistable memory cell elements to set the state of the configuration bits without programming the memory cells of the register. It is thus possible to test the different options in every possible configuration without affecting the memory cells.
2. Description of the Prior Art
An example of a configuration register of this kind is shown in FIG. 1. In this example, the memory is an EPROM type electrically programmable memory whose erasure by ultraviolet rays is prevented by the use of a windowless plastic encapsulation pack. It will be noted that there are other types of one-time programmable memories but they will not be discussed.
The memory (not shown) is usually organized in bit lines (or columns) and word lines (or rows).
A stage of the configuration register corresponding to a bit comprises a bistable stage 1 followed by a static memory stage 2 with inverters.
The bistable stage 1 has two arms Ba and Bb. The first arm Ba is connected to a bit line BLa of the memory by a first transistor T1. The second arm Bb is connected to another bit line BLb by a second transistor T2. These two transistors which are N type transistors in the example are controlled by a signal for the selection of the bistable stage, referenced EPSEL in the figure.
In each arm, there are two transistors and one memory cell series-connected between the logic supply voltage Vcc and the ground. In the example, there is a P type transistor whose source is connected to Vcc and an N type transistor between the P type transistor and the cell. The gate of the P type transistor of one arm is connected to the drain of the N type transistor of the other arm. The gate of the N type transistor of each arm is controlled by the same control signal referenced VDR, whose level is a function of the operation to be performed. The selection transistor associated with an arm is connected to the connection point between the N type transistor and the memory cell of this arm (namely to the drain of the memory cell). The transistor T1 is thus connected to the connection point N1 of the arm Ba and the transistor T2 is connected to the connection point N2 of the arm Bb.
Finally, the memory cells are controlled at their gate by a control signal WL.
The output of the bistable stage 1 is taken at either arm, at the connection point of the two transistors (i.e., in the example at the drain of an N type transistor).
In the arm Ba, between Vcc and the ground, there are thus a P type transistor T3, an N type transistor T4 and a memory cell C1. In the arm Bb, similarly there is a P type transistor T5, an N type transistor T6 and a memory cell C2.
The output S1 of the bistable stage 1 is taken at the node N3 of the arm Bb corresponding to the drain of the transistor T6.
The two cells are blank at the end of manufacture. If a read voltage is applied to their gate (signal WL), then they are on and the output S1 remains at zero volts. If the cell C1 is programmed, the cell C2 remains blank, and the cell C1 goes off, but since the cell C2 is on, the output S1 remains at zero.
If it is the cell C2 that is programmed, with the cell C1 remaining blank, the output S1 will rise substantially to Vcc (in fact Vcc-Vtp, Vtp being the threshold voltage of the P type transistor).
The complementary programming of the memory cells C1 and C2 is done by applying a high programming voltage, generally referenced Vpp, to the bit line associated with the cell to be programmed by means of the switching transistors T1 and T2 and by taking the gate control signal WL of the cells (EPROM memory) to Vpp. At the same time, the gate control signal VDR of the N type transistors is set at zero so as to disconnect the P type and N type transistors of each cell during the programming.
The application of the high voltage to the bit line to be programmed is done in a known way by means of a high voltage switch associated with a data input register for the input of data to be programmed and a bit line address decoder.
The testing means associated with this bistable stage 1 include a static memory stage 2 and means 3 to set the output of the bistable stage at a determined level independently of the memory cell.
The static memory stage 2 includes in a conventional way a first inverter 4 between the terminal Q and a terminal /Q and a second inverter 5 between the terminal /Q and the terminal Q. In the example, the terminal Q is connected to the output S1 of the bistable stage 1 and the terminal /Q is used as an output terminal Bout leading towards the options. A transfer gate PG1 is planned between the output of the second inverter 5 and the Q input of the first inverter. This transfer gate which conventionally has a P type transistor and an N type transistor that are parallel-connected, is controlled by a signal STAT.
In operational mode, the transfer gate PG1 is open (open circuit) and the inverter 4 follows the level of the output S1 of the bistable element with memory cells for the delivery, at output Bout, of a complementary level towards an option configuration input of the integrated circuit.
In the mode for the testing (reading and programming) of the static memory element, the gate PG1 is turned on (closed) to store a specified state with the second inverter.
The testing means include means to set the output level S1 of the bistable element independently of the memory cell. They consist of a transistor parallel-connected with each cell. We thus have the N type transistor T7 parallel-connected with a cell C1 and the N type transistor T8 parallel-connected with the cell C2. These transistors are respectively controlled at their gates by a signal test.sub.a and a signal test.sub.b.
In test mode, these two signals are complementary to one another so that a single transistor is on while the other is off. During this test, the two memory cells have their gates set at zero by the signal WL so that they are off. In this way, it is possible to simulate the two possible states in the bistable state, by turning on either the transistor T7 of the arm Ba or the transistor T8 of the arm Bb. In the static memory element, the transfer gate PG1 is turned on (short-circuited) so that the second inverter 5 confirms the level of S1.
In operational mode, the two signals test.sub.a and test.sub.b are set at zero to turn the two transistors T7 and T8 off.
A structure of this kind proves to be inefficient in practice. Indeed, for each configuration bit, it is necessary to have two test lines: test.sub.a and test.sub.b, with an associated test register. Since a configuration register usually has more than 8 bits, this amounts to a minimum of 16 test lines and two 8-bit test registers. Furthermore, topologically, the memory cells used in the configuration register are located at the end of the bit lines whereas all the registers are brought together at the head of the bit lines.
The making of the structure in practice is therefore highly demanding in terms of requirements of integrated circuit surface area. This entails the necessary limiting (to four, for example) of the number of test lines used to test the bits of the configuration register. There follows a severe limitation of the test cover available since it is no longer possible to test each bit and each option independently of the others.